The present invention relates to data processing systems and more particularly to priority determination techniques used in conjunction with data processing systems.
There are many systems in the prior art which have utilized priority systems. Typically in such systems, data, i.e., bits of a character are transferred in parallel to the respective peripherals for example from a host processor and priority is determined either by for example a location of the peripherals on a common bus or for example by a priority tree structure. Thus, some such priority systems provide a separate priority determination network from the actual data transfer bus in order to provide the priority determination.
In a system requiring a minimum number of cables for interfacing the data processor with a plurality of peripherals seeking access to a data path therebetween, and where the expense of such system must be minimized, it has become evident that some of these prior art techniques cannot be utilized. For example, in such a system where the number of cables must be minimal, data may be transferred bit by bit between the processor and the peripherals. Accordingly, the throughput of the system is minimized and it is thus necessary, in order to provide an acceptable response time in the system, for priority determination to be provided in an efficient manner while utilizing the data transfer bus. Further, the priority of the peripherals must be determined with minimal logic elements while providing relatively fast response.
It is accordingly an object of the invention to provide a priority determination apparatus for use in a data processing system which provides a fast response, which is relatively less complex in construction and relatively inexpensive compared to those priority determination systems of the prior art.
It is a further object of the invention to provide a priority determination technique for use in a data processing system which system includes a bus daisy chained between the processor and a plurality of interface boxes coupling the peripherals with the processor, so that the priority determination and data transfer are accomplished over the same bus.